IMSTW 2005 - Call for Participation

CALL FOR PARTICIPATION

Overview -- Technical Program -- Contacts

Overview

The IEEE International Mixed-Signals Testing Workshop (IMSTW) is a forum for discussing all aspects of testing, design-for-test and reliable design of integrated mixed-signals/mixed-technology circuits and systems. This includes testing and design verification of mixed-signals/mixed-technology circuits (SoC), printed wiring boards and systems-in-packages. The technology spectrum includes analog, mixed-signals, high-speed IO, RF, MEMS, optics and more. Test topics include design-for-test techniques, BIST, fault diagnosis, test generation, on-line and off-line testing, fault modeling, fault simulation, design of fault tolerant systems, mixed-signals infrastructure, and embedded core testing.

Technical Program

top

Monday June 27

8:00-9:00	Registration
9:00-9:15	Welcome and Introduction
9:15-10:00	Invited address	THE MARRIAGE OF MICROELECTRONICS AND PHOTONICS FOR HIGH-SPEED MIXED-SIGNAL PROCESSING APPLICATIONS Kamal Alameh and Adam Osseiran, Edith Cowan University - Perth, Australia.
10:00-10:50	Coffee Break
10:50-12:30	Session S1: Sigma-Delta Test Chair: L. Milor, Georgia Institute of Technology, USA
S1.1.		A DIGITAL BIST FOR AMPLIFIER PARAMETRIC FAULTS IN SD MODULATORS Gildas Leger, Adoracion Rueda, Universidad de Sevilla, Spain
S1.2.		INVESTIGATION INTO THE USE OF ALTERNATIVE TRANSFORMATION TECHNIQUES FOR HIGH-RESOLUTION A/D CONVERTER TESTING Konstantinos Georgopoulos, Andreas Lechner, Martin Burbidge, Andrew Richardson, Lancaster University, U.K.
S1.3.		IMPROVING THE BEHAVIORAL SIMULATION ACCURACY OF THE DESIGN-FOR-DIGITAL-TESTABILITY SECOND-ORDER SIGMA-DELTA MODULATOR Hao-Chiao Hong, National Chiao Tung University, Taiwan
S1.4.		A DIGITAL BIST FOR A 16-BIT AUDIO SIGMA-DELTA ANALOGUE-TO-DIGITAL CONVERTER Luis Rolíndez1,2, Salvador Mir2, Ahcène Bounceur2, Jean-Louis Carbonéro1, 1 ST Microelectronics, Crolles, France, 2 TIMA Laboratory, Grenoble, France
12:30-14:00	Lunch
14:00-15:40	Session S2: Jitter & High-Speed IO Testing Chair: C.L. Wei, NCU, Taiwan
S2.1.		BIST FOR CLOCK JITTER MEASUREMENT OF CHARGE-PUMP PHASE-LOCKED LOOPS JenChien Hsu, Chauchin Su, National Chiao Tung University, Taiwan
S2.2.		LOW-COST PRODUCTION-ORIENTED TESTING FOR PCI-EXPRESS INTERFACE Min-Sheng Lin1, Kwang-Ting Cheng1, Jimmy Hsu 2, MC Sun 2, Jason Chen2, Shelton Lu 2, 1University of California, Santa Barbara, USA, 2VIA Technologies, Hsin-Tien, Taiwan
S2.3.		A BIST SCHEME TO DETECT STRUCTURAL FAULTS IN DELAY-LOCKED-LOOPS Cheng Jia, Linda Milor, Georgia Institute of Technology, Atlanta, USA
S2.4.		NOVEL BIST TECHNIQUE FOR PLL JITTER TOLERANCE VALIDATION IN GIGABIT HIGH-SPEED SERIAL LINKS Chris Siu 1, Kris Iniewski1, I. Filanovsky1, Bozena Kaminska2, 1 University of Alberta, Edmonton, Canada, 2 Simon Fraser University, Burnaby, Canada
15:40-16:10	Coffee Break + Poster Session P1 Chair: E. Simeu, TIMA Laboratory, France
P1.1.		TESTING OF ADCS WITH NOISE SIGNAL Josef Vedral, Jan Holub, Czech Technical University, Prague, Czech Republic
P1.2.		RELIABLE DESIGN OF DIGITAL-TO-ANALOG CONVERTERS USING PRE-CORRECTION AND EMBEDDED SELF-TEST Pieter Harpe, Jacobus de Meulmeester, Hans Hegt, Arthur van Roermund, Eindhoven University of Technology, Eindhoven, The Netherlands
P1.3.		TOWARDS A NEW MODELLING OF MIXED SIGNAL BOARDS FOR MAINTENANCE TESTING Bertrand Gilles1, Valérie-Anne Nicolas1, Lionel Marcé1, Bruno Castel 2, 1Université de Bretagne Occidentale, Brest, France, 2 ISIS-MPP, Brest, France
P1.4.		CONTROLLING TEST PLANS BY INFORMATION-CONTENT-BASED REDUNDANCY ANALYSIS Ivica Rogina1, Hans Martin von Staudt2, Gunther Karner1, 1optimiSE GmbH, Karlsruhe, Germany, 2 Dialog Semiconductor, Kirchheim/Teck, Germany
16:10-17:25	Session S3: Alternate Testing Strategies Chair: A. Rueda, CNM, Spain
S3.1.		ALTERNATE TESTING OF HIGH SPEED A/D CONVERTER DYNAMIC SPECIFICATIONS USING LOW COST TESTER Shalabh Goyal, Abhijit Chatterjee, Georgia Institute of Technology, Atlanta, USA
S3.2.		PREDICTING MIXED-SIGNAL SPECIFICATIONS WITH IMPROVED ACCURACY USING OPTIMIZED SIGNATURES Byoungho Kim1, Hongjoong Shin1, Ji Hwan (Paul) Chun2, Jacob A. Abraham1, 1 University of Texas, Austin, USA, 2 Intel Corporation, Chandler, USA
S3.3.		ROBUST BUILT-IN ALTERNATE TEST OF RF ICS USING ENVELOPE Donghoon Han, Abhijit Chatterjee, Georgia Institute of Technology, Atlanta, USA
18:00-19:00	Welcome Reception

Tuesday June 28

8:30-10:10	Session S4: Fault Simulation and Parameter Identification Chair: B. Kaminska, SFU, Canada
S4.1.		IMPROVING FAULT DICTIONARY TECHNIQUES WITH ARTIFICIAL INTELLIGENCE METHODS FOR LINEAR ELECTRONIC ANALOG CIRCUITS DIAGNOSIS Carles Pous, Joan Colomer, Joaquim Melendez, Universitat de Girona, Spain
S4.2.		PARAMETER IDENTIFICATION BASED DIAGNOSIS IN LINEAR AND NON-LINEAR MIXED-SIGNAL SYSTEMS Emmanuel Simeu, Salvador Mir, TIMA Laboratory, Grenoble, France
S4.3.		FAULT COVERAGE IN A NEW MIXED-SIGNAL VERIFICATION APPROACH Giuseppe Bonfini, Monia Chiavacci, Federico Colucci, Filippo Gronchi, Riccardo Mariani, Egidio Pescari, Andrea Sterpin, Yogitech Spa, Pisa, Italy
S4.4.		A QUASI-STATIC APPROACH FOR DETECTION AND SIMULATION OF PARAMETRIC FAULTS IN ANALOG AND MIXED-SIGNAL CIRCUITS Amir Zjajo, Jose Pineda de Gyvez, Guido Gronthoud, Philips Research Laboratories, Eindhoven, The Netherlands
10:10-10:50	Coffee Break + Poster Session P2 Chair: E. Simeu, TIMA Laboratory, France
P2.1.		RELIABLE DIGITAL CIRCUITS DESIGN USING ANALOG COMPONENTS Erik Schüler, Luigi Carro, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brasil
P2.2.		P2.2. FAULT DIAGNOSIS BASED OF A FINITE-ELEMENT MODEL OF A PIEZORESISTIVE CERAMIC PRESSURE SENSOR Marina Santo Zarnik1, Darko Belavic1, Srecko Macek2, Franc Novak2, 1 HIPOT-R&D, Sentjernej, Slovenia, 2 Jozef Stefan Institute, Ljubljana, Slovenia
P2.3.		ENABLING TEST-TIME OPTIMIZED PSEUDORANDOM BIT STREAM (PRBS) 231 BER testing on Automated Test Equipment for 10Gbps device Shao Chee Ong, Intel Technology Sdn Bhd, Penang, Malaysia
10:50-12:30	Session S5: RF Testing Chair: G. Gronthoud, Philips, The Netherland
S5.1.		A NEW DFT/DFM PARADIGM FOR TESTING COMPLEX RFICS Yu Miao, Elida de-Obaldia, Texas Instruments, Dallas, USA
S5.2.		BUILT-IN SENSORS AND TESTING TECHNIQUE FOR RF AMPLIFIERS Hsieh-Hung Hsieh, Liang-Hung Lu, National Taiwan University, Taipei, Taiwan
S5.3.		PRODUCTION TEST ENHANCEMENT FOR MB-OFDM ULTRA-WIDE BAND (UWB) TRANSMITTER SPECIFICATIONS: EVM AND CCDF Soumendu Bhattacharya, Rajarajan Senguttuvan, Abhijit Chatterjee, Georgia Institute of Technology, Atlanta, USA
S5.4.		A TECHNIQUE FOR IN-CIRCUIT TESTING OF LNAS José Machado da Silva, Universidade do Porto, Portugal
12:30-14:00	Lunch
14:00-15:40	Session S6: MEMS Testing Chair: B. Courtois, TIMA Laboratory, France
S6.1.		SUPERPOSITION VS. MODULATION: A COMPARATIVE ANALYSIS FOR ELECTRO THERMAL ON LINE MEMS TESTING Frédérick Mailly, Florence Azaïs, Norbert Dumas, Laurent Latorre, Pascal Nouet, LIRMM, Montpellier, France
S6.2.		DESIGN CONSIDERATIONS FOR ON-LINE TESTING OF A CAPACITIVE ACCELEROMETER Carl Jeffrey1, R.J.T. Bunyan2, D. Combes 2, D. O. King2, A.M.D. Richardson1, 1 Lancaster University, U.K., 2 Qinetiq, Malvern, U.K.
S6.3.		NONLINEARITY EFFECTS ON MEMS ON-CHIP PSEUDORANDOM TESTING Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur, TIMA Laboratory, Grenoble, France
S6.4.		DESIGN & TEST OF AN OSCILLATION BASED SYSTEM ARCHITECTURE FOR DNA SENSOR ARRAYS Hongyuan Liu1, Hans G. Kerkhoff2, Andrew Richardson1, Xiao Zhang2, Pascal Nouet3, Florence Azais3, 1 Lancaster University, U.K., 2 University of Twente, The Netherlands, 3 LIRMM, Montpellier, France
15:40-16:00	Coffee Break
16:00-17:15	Panel Session	FROM SELF-CALIBRATION TO SELF-TUNING TO SELF-REPAIR FOR MIXED-SIGNALS COMPONENTS: IS THIS THE RIGHT DIRECTION ?
17:45	Social Event / Banquet

Wednesday June 29

8:30-10:10	Session S7: Converter Testing Chair: A. Chatterjee, Georgia Institute of Technology, USA
S7.1.		FAST AND FULLY-EFFICIENT TEST FLOW FOR ADCS Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell, LIRMM, Montpellier, France
S7.2.		OPTIMIZATION OF FPGA BASED TEST STRATEGY FOR HIGH RESOLUTION ADC Daniela De Venuto1, Francesco Dell'Olio1, Leonardo Reyneriy2, 1 Politecnico di Bari, Italy, 2 Politecnico di Torino, Italy
S7.3.		DSP-BASED BUILT-IN SELF-TEST: APPLICATION TO DYNAMIC CHARACTERIZATION OF DATA CONVERTERS Haksoo Yu1, Jacob A. Abraham2, T.M. Mak3, 1 Samsung Corporation, 2 University of Texas, Austin, USA, 3 Intel Corporation
S7.4.		COMPARISON BETWEEN SPECTRAL-BASED METHODS FOR INL ESTIMATION AND FEASIBILITY OF THEIR IMPLEMENTATION Vincent Kerzérho1,2, Serge Bernard1, Jean-Marie Janik3, Philippe Cauvet2, 1 LIRMM, Montpellier, France, 2 Philips Semiconducteurs, Caen, France, 3 University of Caen, France
10:10-10:50	Coffee Break + Poster Session P3 Chair: E. Simeu, TIMA Laboratory, France
P3.1.		SELF CHECKING CIRCUITS FOR SECURITY APPLICATIONS Julian Murphy, Alex Bystrov, Alex Yakovlev, University of Newcastle upon Tyne, U.K.
P3.2.		TEST OF AVERAGED PREAMPLIFIERS IN FOLDED ADCS Roman Mozuelos, Yolanda Lechuga, Mar Martinez, Salvador Bracho, University of Cantabria, Santander, Spain
P3.3.		STRESS TEST OF CMOS SRAMS FOR RELIABILITY ENHANCEMENT Chin-Long Wey1, Meng-Yao Liu1, Shaolei Quan2, 1 National Central University, Chung-Li, Taiwan, 2 Michigan State University, East Lansing, USA
10:50-12:30	Session S8: Reliability & Testability Analysis Chair: J. Figueras, UPC, Spain
S8.1.		TESTABILITY ANALYSIS FOR TRUE MIXED-SIGNAL INTEGRATED CIRCUITS Araldo van de Kraats, Hans G. Kerkhoff, MESA+ Institute for Nanotechnology, Enschede, The Netherlands
S8.2.		SIGMA-DELTA MODULATORS ON THE DESIGN OF RELIABLE DIGITAL CIRCUITS Erik Schüler, Luigi Carro, Universidade Federal do Rio Grande do Sul, Brasil
S8.3.		TOWARDS FAULT-TOLERANT RF FRONT-ENDS: ON-CHIP INPUT MATCH SELF-CORRECTION OF LNAS Tejasvi Das, Anand Gopalan, Clyde Washburn, P.R. Mukund, Rochester Institute of Technology, USA
S8.4.		ANALYSIS OF THE IMPACT OF PROCESS VARIATIONS ON OSCILLATION TEST METHODOLOGIES Rodrigo Picos, Miquel Roca, Sebastian Bota, Eugeni Isern, Kay Suenaga, Eugeni Garcia, Universitat Illes Balears, Palma, Spain
12:30-14:00	Lunch
14:00-15:15	Session S9: BIST and On-Chip Self-Tuning Chair: Chau-Chin Su, NCU, Taiwan
S9.1.		AN ON-CHIP RANDOM JITTER TESTING TECHNIQUE USING LOW TAP-COUNT DELAY LINES Jiun-Lang Huang, National Taiwan University, Taipei, Taiwan
S9.2.		ON CHIP SELF-TUNING OF HIGH PERFORMANCE FILTERS VIA PSEUDO-RANDOM INPUT TEST SIGNAL Gianvito Matarrese1, Cristoforo Marzocca1, Stefano D'Amico2, Francesco Corsi1, Andrea Baschirotto2, 1 Politecnico di Bari, Italy, 2 Universita di Lecce, Italy
S9.3.		FLOATING GATE MONITOR FOR MIXED-SIGNAL LISSAJOUS BASED BIST Ricard Sanahuja, Victor Barcons, Luz Balado, Joan Figueras, Universitat Politecnica de Catalunya, Barcelona, Spain
15:15-15:30	Closing Session

Contacts

top

General Chair S. Mir TIMA Laboratory 46 Av. Félix Viallet, 38031 Grenoble, France E-mail: Salvador.Mir@imag.fr
*Program Co-Chair* A. Richardson Lancaster University Bailrigg Lancaster, UK-LA1 4YR Lancaster, UK E-mail : a.richardson@lancaster.ac.uk	*Program Co-Chair* K.-T. Cheng Electrical and Computer Eng. Department University of California Santa Barbara, CA 93106-9560,USA E-mail: timcheng@ece.ucsb.edu
*Local Chair* L. Rufer TIMA Laboratory 46 Av. Félix Viallet, 38031 Grenoble, France E-mail: Libor.Rufer@imag.fr

For more information, visit us on the web at: http://tima.imag.fr/conferences/IMSTW05/

The 11th Annual International Mixed-Signals Testing Workshop (IMSTW'05) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).